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1 white electronic designs corporation ? phoenix, az ? (602) 437-1520 hi-reliability product we32k32-xxx 32kx32 eeprom module, smd 5962-94614 features n access times of 80*, 90, 120, 150ns n mil-std-883 compliant devices available n packaging: ? 68 lead, hermetic cqfp (g2u), 22.4mm (0.880") square, 3.56mm (0.140") height (package 510). designed to fit jedec 68 lead 0.990" cqfj footprint (fig. 2) ? 66-pin, pga type, 1.075" square, hermetic ceramic hip (package 400) n data retention at 25 c, 10 years n write endurance, 10,000 cycles n organized as 32kx32; user configurable 64kx16 or 128kx8 n commercial, industrial and military temperature ranges n automatic page write operation n page write cycle time: 10ms max n data polling for end of write detection n hardware and software data protection n ttl compatible inputs and outputs n 5 volt power supply n low power cmos, 10ma standby typical n built-in decoupling caps and multiple ground pins for low noise operation * 80ns speed is not fully characterized and is subject to change or cancellation without notice. pin description fig. 1 pin configuration for we32k32n-xh1x top view i/o 8 i/o 9 i/o 10 a 13 a 14 nc nc nc i/o 0 i/o 1 i/o 2 we 2 cs 2 gnd i/o 11 a 10 a 11 a 12 v cc cs 1 nc i/o 3 i/o 15 i/o 14 i/o 13 i/o 12 oe nc we 1 i/o 7 i/o 6 i/o 5 i/o 4 i/o 24 i/o 25 i/o 26 a 6 a 7 nc a 8 a 9 i/o 16 i/o 17 i/o 18 v cc cs 4 we 4 i/o 27 a 3 a 4 a 5 we 3 cs 3 gnd i/o 19 i/o 31 i/o 30 i/o 29 i/o 28 a 0 a 1 a 2 i/o 23 i/o 22 i/o 21 i/o 20 11 22 33 44 55 66 1 12 23 34 45 56 i/o 0-31 data inputs/outputs a 0-14 address inputs we 1-4 write enables cs 1-4 chip selects oe output enable v cc power supply gnd ground nc not connected 32k x 8 8 i/o 0-7 we cs 1 1 32k x 8 8 i/o 8-15 we cs 2 2 32k x 8 8 i/o 16-23 we cs 3 3 32k x 8 8 i/o 24-31 we cs 4 4 a 0-14 oe block diagram june 1999 rev. 2
2 white electronic designs corporation ? phoenix, az ? (602) 437-1520 we32k32-xxx 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 v cc a 11 a 12 a 13 a 14 nc nc cs 1 oe cs 2 nc we 2 we 3 we 4 nc nc nc i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 gnd i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 nc a 0 a 1 a 2 a 3 a 4 a 5 cs 3 gnd cs 4 we 1 a 6 a 7 a 8 a 9 a 10 v cc pin description i/o 0-31 data inputs/outputs a 0-14 address inputs we 1-4 write enables cs 1-4 chip selects oe output enable v cc power supply gnd ground nc not connected fig. 2 pin configuration for we32k32-xg2ux block diagram 32k x 8 8 i/o 0-7 we cs 1 1 32k x 8 8 i/o 8-15 we cs 2 2 32k x 8 8 i/o 16-23 we cs 3 3 32k x 8 8 i/o 24-31 we cs 4 4 a 0-14 oe top view the white 68 lead g2u cqfp fills the same fit and function as the jedec 68 lead cqfj or 68 plcc. but the g2u has the tce and lead inspection advantage of the cqfp form. 0.940"
3 white electronic designs corporation ? phoenix, az ? (602) 437-1520 we32k32-xxx absolute maximum ratings dc characteristics (v cc = 5.0v, gnd = 0v, t a = -55 c to +125 c) truth table note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions capacitance (t a = 25 c) fig. 3 ac test circuit ac test conditions i current source d.u.t. c = 50 pf eff i ol v 1.5v (bipolar supply) z current source oh notes: v z is programmable from -2v to +7v. i ol & i oh programmable from 0 to 16ma. tester impedance z 0 = 75 w . v z is typically the midpoint of v oh and v ol . i ol & i oh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance. cs oe we mode data i/o h x x standby high z l l h read data out l h l write data in x h x out disable high z/data out x x h write x l x inhibit parameter symbol unit operating temperature t a -55 to +125 c storage temperature t stg -65 to +150 c signal voltage relative to gnd v g -0.6 to +6.25 v voltage on oe and a9 -0.6 to +13.5 v parameter symbol min max unit supply voltage v cc 4.5 5.5 v input high voltage v ih 2.0 v cc + 0.3 v input low voltage v il -0.5 +0.8 v operating temp. (mil.) t a -55 +125 c operating temp. (ind.) t a -40 +85 c parameter symbol condition max unit address input capacitance c ad v in = 0v, f = 1.0mhz 50 pf oe capacitance c oe cs 1-4 capacitance c cs v in = 0v, f = 1.0mhz 20 pf we 1-4 capacitance c we v in = 0v, f = 1.0mhz 20 pf data i/ o capacitance c i/o v in = 0v, f = 1.0mhz 20 pf this parameter is guaranteed by design but not tested. parameter symbol conditions -80 -90 -120 -150 units min max min max min max min max input leakage current i li v cc = 5.5, v in = gnd to v cc 10 10 10 10 m a output leakage current i lo x 32 cs = v ih , oe = v ih , v out = gnd to v cc 10 10 10 10 m a operating supply current x 32 mode i cc x 32 cs = v il , oe = v ih , f = 5mhz 320 250 200 150 ma standby current i sb cs = v ih , oe = v ih , f = 5mhz 2.5 2.5 2.5 2.5 ma output low voltage v ol i ol = 2.1ma, v cc = 4.5v 0.45 0.45 0.45 0.45 v output high voltage v oh i oh = -400 m a, v cc = 4.5v 2.4 2.4 2.4 2.4 v note: dc test conditions: v ih = v cc -0.3v, v il = 0.3v parameter typ unit input pulse levels v il = 0, v ih = 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v
4 white electronic designs corporation ? phoenix, az ? (602) 437-1520 we32k32-xxx a write cycle is initiated when oe is high and a low pulse is on we or cs with cs or we low. the address is latched on the falling edge of cs or we whichever occurs last. the data is latched by the rising edge of cs or we, whichever occurs first. a byte write operation will automatically continue to completion. write write cycle timing figures 4 and 5 show the write cycle timing relationships. a write cycle begins with address application, write enable and chip select. chip select is accomplished by placing the cs line low. write enable consists of setting the we line low. the write cycle begins when the last of either cs or we goes low. the we line transition from high to low also initiates an internal 150 m sec delay timer to permit page mode operation. each subsequent we transition from high to low that occurs before the completion of the 150 m sec time out will restart the timer from zero. the operation of the timer is the same as a retriggerable one-shot. ac write characteristics (v cc = 5.0v, gnd = 0v, t a = -55 c to +125 c) write cycle -80 -90 -120 -150 write cycle parameter symbol min max min max min max min max unit write cycle time, typ = 6ms t wc 10 10 10 10 ms address set-up time t as 0 0 30 30 ns write pulse width (we or cs) t wp 100 100 150 150 ns chip select set-up time t cs 000 0 ns address hold time t ah 50 50 100 100 ns data hold time t dh 0 0 10 10 ns chip select hold time t csh 000 0 ns data set-up time t ds 50 50 100 100 ns write pulse width high t wph 50 50 50 50 ns output enable set-up time t oes 10 10 10 10 ns output enable hold time t oeh 10 10 10 10 ns
5 white electronic designs corporation ? phoenix, az ? (602) 437-1520 we32k32-xxx fig. 4 write waveforms we controlled fig. 5 write waveforms cs controlled t address cs 1-4 we 1-4 data in dh t wph t wp t csh t oeh t ah t oes t as t cs oe t wc t ds t address we 1 - 4 cs 1 - 4 data in dh t wph t wp t csh t oeh t ah t oes t as t cs oe t ds t wc
6 white electronic designs corporation ? phoenix, az ? (602) 437-1520 we32k32-xxx read the we32k32-xhx stores data at the memory location determined by the address pins. when cs and oe are low and we is high, this data is present on the outputs. when cs and oe are high, the outputs are in a high impedance state. this 2 line control prevents bus contention. ac read characteristics (see figure 6) (v cc = 5.0v, gnd = 0v, t a = -55 c to +125 c) fig. 6 read waveforms notes: 1. oe may be delayed up to t acs - t oe after the falling edge of cs without impact on t oe or by t acc - t oe after an address change without impact on t acc . 2. t chz , t ohz are specified from oe or cs whichever occurs first (c l = 5pf). 3. all i/o transitions are measured 200 mv from steady state with loading as specified in "load test circuits." t address cs oe output oh t df t acc t rc t oe t acs output valid address valid high z read cycle symbol -80 -90 -120 -150 unit parameter min max min max min max min max read cycle time t rc 80 90 120 150 ns address access time t acc 80 90 120 150 ns cs access time t acs 80 90 120 150 ns output hold from add. change, oe or cs t oh 0000ns output enable to output valid t oe 40 50 85 85 ns chip select or oe to output in high z t df 40 50 70 70 ns
7 white electronic designs corporation ? phoenix, az ? (602) 437-1520 we32k32-xxx data polling the we32k32-xxx offers a data polling feature which allows a faster method of writing to the device. figure 7 shows the timing diagram for this function. during a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on d 7 (for each chip.) once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the write cycle. fig. 7 data polling waveforms data polling characteristics (v cc = 5.0v, gnd = 0v, t a = -55 c to +125 c) parameter symbol min max unit data hold time t dh 10 ns oe hold time t oeh 10 ns oe to output valid t oe 100 ns write recovery time t wr 0ns we 1-4 t oeh t dh t oe t wr high z cs 1-4 oe i/o 7 address
8 white electronic designs corporation ? phoenix, az ? (602) 437-1520 we32k32-xxx page write operation the we32k32-xxx has a page write operation that allows one to 64 bytes of data to be written into the device and consecutively loads during the internal programming period. successive bytes may be loaded in the same manner after the first data byte has been loaded. an internal timer begins a time out operation at each write cycle. if another write cycle is completed within 150 m s or less, a new time out period begins. each write cycle restarts the delay period. the write cycles can be continued as long as the interval is less than the time out period. page write characteristics (v cc = 5.0v, gnd = 0v, t a = -55 c to +125 c) page mode write characteristics parameter symbol -80 -90 -120 -150 unit min max min max min max min max write cycle time, typ = 6ms t wc 10 10 10 10 ms data set-up time t ds 50 50 100 100 ns data hold time t dh 0 0 10 10 ns write pulse width t wp 100 100 150 150 ns byte load cycle time t blc 150 150 150 150 m s write pulse width high t wph 50 50 50 50 ns the usual procedure is to increment the least significant address lines from a0 through a5 at each write cycle. in this manner a page of up to 64 bytes can be loaded in to the eeprom in a burst mode before beginning the relatively long interval programming cycle. after the 150 m s time out is completed, the eeprom begins an internal write cycle. during this cycle the entire page of bytes will be written at the same time. the internal programming cycle is the same regardless of the number of bytes accessed. fig. 8 page write waveforms note: 1. decoded address lines must be valid for the duration of the write. oe cs we address (1) data byte 0 byte 1 byte 2 byte 3 byte n byte n + 1 valid data valid address t wc t blc t wph t wp t dh t ds
9 white electronic designs corporation ? phoenix, az ? (602) 437-1520 we32k32-xxx load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data xx to any address (4) load last byte to last address t t t t writes enabled (2) enter data protect state fig. 9 software block data protection enable algorithm (1) notes: 1. data format: d 7 - d 0 (hex); address format: a 14 - a 0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64 bytes of data may be loaded.
10 white electronic designs corporation ? phoenix, az ? (602) 437-1520 we32k32-xxx software data protection a software write protection feature may be enabled or disabled by the user. when shipped by white microelectronics, the we32k32-xxx has the feature disabled. write access to the device is unrestricted. to enable software write protection, the user writes three access code bytes to three special internal locations. once write protection has been enabled, each write to the eeprom must use the same three byte write sequence to permit writing. after setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. no data will be written to the device, however, for the duration of t wc . the write protection feature can be disabled by a six byte write sequence of specific data to specific locations. power transitions will not reset the software write protection. each 32kbyte block of the eeprom has independent write protection. one or more blocks may be enabled and the rest disabled in any combination. the software write protection guards against inadvertent writes during power transitions, or unauthorized modification using a prom programmer. hardware data protection these features protect against inadvertent writes to the we32k32-xxx. these are included to improve reliability during normal operation: a) v cc power on delay as v cc climbs past 3.8v typical the device will wait 5msec typical before allowing write cycles. b) v cc sense while below 3.8v typical write cycles are inhibited. c) write inhibiting holding oe low and either cs or we high inhibits write cycles. d) noise filter pulses of <8ns (typ) on we or cs will not initiate a write cycle. fig. 10 software block data protection disable algorithm (1) t t t t t t t (3) notes: 1. data format: d 7 - d 0 (hex); address format: a 14 - a 0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64 bytes of data may be loaded. exit data protect state (3) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 20 to address 5555 load data xx to any address (4) load last byte to last address
11 white electronic designs corporation ? phoenix, az ? (602) 437-1520 we32k32-xxx package 400: 66 pin, pga type, ceramic hex-in-line package, hip (h1) 27.3 (1.075) 0.25 (0.010) sq pin 1 identifier square pad on bottom 25.4 (1.0) typ 15.24 (0.600) typ 0.76 (0.030) 0.13 (0.005) 4.34 (0.171) max 3.81 (0.150) 0.13 (0.005) 2.54 (0.100) typ 25.4 (1.0) typ 1.42 (0.056) 0.13 (0.005) 1.27 (0.050) typ dia 0.46 (0.018) 0.05 (0.002) dia all linear dimensions are millimeters and parenthetically in inches
12 white electronic designs corporation ? phoenix, az ? (602) 437-1520 we32k32-xxx package 510: 68 lead, ceramic quad flat pack, cqfp (g2u) 0.38 (0.015) 0.05 (0.002) 0.25 (0.010) 0.10 (0.002) 25.15 (0.990) 0.25 (0.010) sq 1.27 (0.050) typ 24.0 (0.946) 0.25 (0.010) 22.36 (0.880) 0.25 (0.010) sq 20.3 (0.800) ref 23.87 (0.940) ref 1.01 (0.040) 0.13 (0.005) 0.25 (0.010) ref 1 / 7 r 0.25 (0.010) detail a see detail "a" pin 1 0.53 (0.021) 0.18 (0.007) 3.51 (0.140) max all linear dimensions are millimeters and parenthetically in inches 0.940" typ the white 68 lead g2u cqfp fills the same fit and function as the jedec 68 lead cqfj or 68 plcc. but the g2u has the tce and lead inspection advantage of the cqfp form.
13 white electronic designs corporation ? phoenix, az ? (602) 437-1520 we32k32-xxx ordering information lead finish: blank = gold plated leads a = solder dip leads device grade: q = mil-std-883 compliant m = military screened -55 c to +125 c i = industrial -40 c to +85 c c = commercial 0 c to +70 c package type: h1 = ceramic hex in-line package, hip (package 400) g2u = 22.4mm ceramic quad flat pack, cqfp low profile (package 510) access time (ns) improvement mark n = no connect at pins 8, 21, 28, and 39 in hip for upgrade organization, 32k x 32 user configurable as 64kx16 or 128kx8 eeprom white electronic designs corp. device type speed package smd no. 32k x 32 eeprom module 150ns 66 pin hip (h1) 5962-94614 01hxx 32k x 32 eeprom module 120ns 66 pin hip (h1) 5962-94614 02hxx 32k x 32 eeprom module 90ns 66 pin hip (h1) 5962-94614 03hxx 32k x 32 eeprom module 150ns 68 lead cqfp/j (g2u) 5962-94614 01hzx 32k x 32 eeprom module 120ns 68 lead cqfp/j (g2u) 5962-94614 02hzx 32k x 32 eeprom module 90ns 68 lead cqfp/j (g2u) 5962-94614 03hzx w e 32k32 x - xxx x x x

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